Phase detector assembly



Nov. 16, 1965 JAMES E. WEBB 3,218,479

ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION PHASEDETECIDR ASSEMBLY Filed Feb. 28, 1963 6 Sheets-Sheet l ,ss COUNTER 9/. zTUNNEL DIODE 40 73 .6 4 J as o I I I l l I I I I I a) FIG. 2 l2 TUNNELDIODE 4s .6

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ATTORNEYS Nov. 16, 1965 JAMES E. WEBB 3,

ADMINISTRATOR OF THE NATIONAL AERONAUTICS AN D SPACE ADMINISTRATIONPHASE DETECTOR ASSEMBLY Filed Feb. 28, 1965 6 heet -Sheet 2 )j A II 3 mo 5 3 w "(9 3h wl-L d '2 g-u. (\l o' v o' w r N 238S gi'g'o oo' A A S Vv V O o 10 l0 3? 0 G a .0 N Ll LL GORDON D. ANDERSON,

IN VEN TOR.

AT TORNE'YS Nov. 16, 1965 ADMINISTRATOR OF THE NATIONAL AERONAUTICS ANDSPACE ADMINISTRATIQN PHASE DETECTOR ASSEMBLY Filed Feb. 28, 1963 "HIGH"L6 2.0 2.4 IV.)

FIG.9

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JAMES E. WEBB 6 Sheets-Sheet 5 GORDON D. ANDERSON IN VEN TOR.

BY jwz;

ATTORNEYS Nov. 16, 1965 JAMES WEBB 3,218,479

ADMINISTRATOR OF THE NATIONAL AERQNAUTICS AND SPACE ADMINISTRATION PHASEDETECTOR ASSEMBLY GORDON D. ANDERSON,

INVENTOR.

BY Ch 7% ATTORNEYS TICS N 1965 JAMES E. WEBB ADMINISTRATOR OF THENATIONAL AERONAU AND SPACE ADMINISTRATION PHASE DETECTOR ASSEMBLY 6Sheets-Sheet 5 Filed Feb. 28, 1963 D oi 33 m6 To 0N F V GORDON D.ANDERSON INVENTOR.

flaw CA 7% 1 -1 ATTORNEYS NOV. 16, 1965 JAMES 5, 553 3,218,479

ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADMINISTRATION PHASEDETECTOR ASSEMBLY Filed Feb. 28, 1963 6 Sheets-Sheet 6 TIME INNANOSECONDS .6 FIG. l9

0 v I I 1 l TIME IN NANOSECONDS FIG. 20

GORDON D. ANDERSON,

IN V EN TOR.

BY KL M/Q-M 6 4255%.

ATTORNEYS United States Patent 3,218,479 PHASE DETECTOR ASSENBLY JamesE. Webb, Administrator of the National Aeronautics and SpaceAdministration, with respect to an invention of Gordon D. Anderson FiledFeb. 28, 1963, Ser. No. 261,917 4 Claims. (Cl. 30788.5)

This invention relates to the art of electrical signal processing andparticularly to means for discriminating with respect to a first signalin terms of the presence or absence of a second signal at the time ofoccurrence of the first signal.

It has been found necessary in certain applications of very highfrequency generators, frequency multipliers and dividers to determinetheir short time, cycle to cycle, stability or accuracy, it having beenfound that information as to the long-time or statistical accuracy ofthese devices, which may be excellent, is an inadequate guide as totheir short term accuracy. It will be appreciated that short termaccuracy becomes more important as information is electrically processedat higher and higher rates.

It has further been found that short term signal disturbances due, forexample to electrical noise, are manifested by wave form distortions andthat the extent of distortion can be related as a phase measurement bycomparison with a signal from a frequency standard operating at the samefrequency, at a multiple frequency or submultiple frequency.

Phase measurement or comparison is, in accordance with this invention,accomplished by means which combine the functions of anticoincidencedetection with signal sampling in a manner which compares the time ofoccurrence of the leading edges of the two wave forms compared. If thewave form of interest coincides with or lags the reference wave it willbe inhibited and no output will be produced. If the wave form ofinterest leads the reference wave form an output will be produced. Bymeans of a conventional counter it is possible to distinguish theseconditions on a cycle for cycle basis.

While it was first concluded that the above functions could have beenachieved by a combination of several devices such as and circuitry forgating and coincidence detection with multivibrator flip-flops providingsignal sampling and lock-out, it was conceived and determined that thesefunctions could be performed by a much simpler combination of circuitelements.

In accordance with these findings, the invention, an electricaldiscriminator or phase detector assembly, employs two nonlinear circuitseach of which includes a resistive element and atwo terminal nonlinearcircuit means, such as a tunnel diode, which provides a first and secondpositive resistance operating regions separated by a negative resistanceregion, the nonlinear circuits being common to the extent of one of thenonlinear means which has a higher current peak (a factor ofapproximately 2 produces excellent operation) to its first positiveresistance region than the other nonlinear means. Biasing means, such asa direct current source and a resistance element in series, areconnected across the nonlinear means in a polarity to bias bothnonlinear means to a point of operation in their first (lower voltage)positive resistance regions. Sensing means such as an electrical pulsecounter to read-out the output of the discriminator is connected acrossthe uncommon nonlinear means through such resistance as to preventsignificant loading effects upon the discriminator.

The objectives, features and advantages of the present invention willbecome more apparent from the following discription when consideredtogether with the accompanying drawings in which:

"ice

FIGURE 1 is a schematic circuit diagram of an embodiment of theinvention; and

FIGURES 2-20 are graphical representations of characteristics ofoperation of the embodiment shown in FIG- URE 1.

Referring now to the drawings and initially to FIG- URE 1, inputterminal connected to a common point or ground 32 and input terminal 34provides a first circuit input across which is applied a first signal 35from first generator 36 through adjustable delay line 37 which is apulse train (e.g. 10 mc.) having a positive pulse amplitude of 5 volts(at terminal 34 with respect to terminal 30) producing current pulses 1The first circuit input is connected through input resistor 38 (e.g.2700 ohms) across tunnel diode 40 (e.g. 1N2969), resistor 38 beingconnected between terminal 34 and the cathode terminal 39 of tunneldiode 40. The anode terminal 41 of tunnel diode 40 is connected tocircuit ground. Current pulses I, thus flow through a first circuit orcircuit leg from terminal 34 to ground 32.

A second circuit input is provided by input terminals 42 and 30 acrosswhich is applied a second signal 44 from second generator 45 to becompared with the first signal 35. The second signal is an alternatingcurrent pulse wave (e.g. 1 me.) having an amplitude of 2.5 volts and apeak-to-peak voltage of 5 volts (the same as generator 36). This secondcircuit is connected through resistor 46 across tunnel diodes 48 (e.g.1N2939) and 40 in series. Resistor 46 connects between terminal 42 andthe cathode terminal 49 of tunnel diode 48, and the anode terminal 50 oftunnel diode 48 connects to the cathode terminal 39 of tunnel diode 40.Diode 40 is chosen to have a higher peak current characteristic (e.g.approximately double) than diode 48. Current pulses I flow from terminal42 to terminal 30 when the polarity of the input is positive at terminal42 with respect to terminal 30. Of the diodes cited as examples, diode40 has a tunnel region peak current of approximately 2.2 milliamperes(ma) and diode 48 of approximately 1 milliampere.

A biasing circuit consisting of a direct current source (e.g. 1 volt) 51in series with resistor 52 (e.g. 2000 ohms) is connected across tunneldiodes 40 and 48 which raises the current operating point of diode 48 toa point on its first positive resistance, which is about half the valueof its peak point current (a point dividing the first positiveresistance region from the negative resistance region). Thus, resistor46 is on the order of half again the value of resistor 38 and resistor46 is on the order of double the value of resistor 52.

The output of the discriminator is obtained across diode 48 and appearsat output terminals 54 and 56 from which it is applied to a pulsecounter 58 such as would include standard means for amplifying (e.g. abroad band differential amplifier would be employed to drive standardcommercial counters), counting and printing out a pulse count. Inaddition to the counter the discriminator assembly as a whole includesresistors 60 and 62 (e.g. 10,000 ohms each) which are connected one inseries with each output terminal to help isolate output circuitry, suchas counter 58, from the discriminator and prevent loading effects, asfrom lower impedance output circuitry, from effecting discriminatoroperation. Resistor 60 connects between terminal 54 and the cathode ofdiode 48 and resistor 62 connects between terminal 56 and the anode ofdiode 48.

To examine the operation of the circuitry, assume first that neither ofthe input signals are present. The discriminator output, which appearsacross tunnel diode 48, is then governed 'by the current through theseries circuit consisting of source 51, resistor 52 and diodes 48 and40. Since the current cannot exceed ,5 milliampere (ma) through thiscircuit due to the 2000 ohms resistance of resistor 52 alone, it appearsfrom FIGURES 2 and 3 showing the approximate current-voltagecharacteristics of diodes 40 and 48, respectively, that the voltagedrops and thus the resistance will be quite small with respect to theresistance of resistor 52. This indicates that the current through diode48 will be just slightly below .5 ma. and this point is plotted from thebias load line 64 of FIG- URE 4, as point 65 on FIGURE 3 resulting in aninitial or resting, output voltage across diode 48 of approximately .02volt, for a no signal condition. Thus diodes 40 and 48 both remain intheir low voltage regions 53 and 55, respectively.

Next, assume that the first signal or pulse train 35 is applied acrossthe first input between terminals 34 and 30 and is undelayed byadjustable delay line 37. This in turn has the effect of increasing thecurrent through diode 40 as this applied signal is connected throughresistor 38 across diode 40. To determine the current now through diode48 load line 64, and load line 66 representative of first input circuit67 (source labeled 35(a) represents D.C. equivalent for signal 35),shown in FIGURE 5, are combined as load line 69 in FIGURE 6. 69 onFIGURE 2, it is seen that the current through diode 40 would beapproximately 2.3 ma. and exceeds the peak current 1p for diode 40. Theresult is that diode 40 flips from its low voltage state 72 is point 73.From point 73, the intersection of load line 69 and the characteristiccurve of diode 40, it will be seen that the current through diode 40 isnow approximately 1.9 ma. with a voltage drop of approximately .49 volt.

With this increased voltage drop in the series circuit through diode 48it is significant to examine the effect on the output voltage. Turningto FIGURE 4,. a modified load line 75 (shown in broken line) is drawnfrom a source voltage of approximately .5 volt (instead of 1 volt),representing the net voltage applied to the bias circuit with thesubtraction of the voltage now across diode 40 from the voltage ofsource 51. Plotting load line 75 on FIGURE 3, it appears fromintersecting point 77 that there has occurred a decrease in outputvoltage, across diode 48, of from approximately .02 volt to .01 volt, avery slight change, however, compared to changes which, as will beshown, occur when inputs occur in the proper order for response (Ileading I Accordingly, it may be concluded that a signal acrossterminals 34 and 30 alone does not produce a significant output.

Next, the case is considered where signal 44 is applied to the secondinput in the presence of signal 35 applied to the first input. Signal 44should be the lower frequency if the input signals are of differentfrequency (if different, signal 35 should be integral multiple of signal44) and here we will assume that signal 35 is at megacycle rate andsignal 44 is a 1 megacycle rate. With the occurrence of a positive halfcycle of signal 44, current through diode 48 increases and in accordancewith FIGURE 3 the voltage increases.

Current flowing in diode 48 is the result of the bias plotted as loadline 75 in FIGURE 4 and the signal voltage (2.5 volt source 44(a)representative of signal 44, and source 40(a) representative of voltageacross diode 40) plotted as load line 79 in FIGURE 7. The sources arerepresented schematically as batteries for this instantaneous case. Thecomposite load line 81 of load lines 75 and 79, shown in FIGURE 8, isreplotted in FIGURE 3. As will be noted, the resulting current in diode48 is shown at point 83 as approximately .61 ma. at a drop ofapproximately .025 volt, demonstrating that diode 48 is not raised toits high voltage state by the presence of both signals, signal 35 havingoccurred first. In fact, the voltage across diode 48 does not changesignificantly.

At the end of the first cycle of first signal 35 (point 85), currentfrom this source will drop to zero but diode 48 must remain in the lowvoltage state (no output) even in the presence of signal 44 if theintended logic is to Plotting load linebe preserved. If diode 40 ismaintained in its high voltage state by current from second signal 44,the voltage drop across diode 40 will reduce current flow through bothdiodes such that current through diode 48 will be lIlSlJl'fiClCl'lt toraise diode 48 to its high voltage state as already shown. In thismanner, output which would be provoked by the presence of second signal44 alone or occurring first is prevented.

The combined voltage drop, across both diodes, is plotted in FIGURE 9 ascurve 87, diode 40 being in a high state or forward region 72 (FIGURE 2)and diode 48 being in a low voltage state 55. Curve 87 is plottedbetween current limits of the valley point 88 of diode 40 and the peakpoint Ip of diode 48. Load lines for resistor 52 (load line 64) in biascircuit 65, and for resistor 46 in input circuit 89 (resistor 46 andsource 44a) are plotted in FIGURES 4 and 10 (load line 90),respectively, and their combined current is plotted as curve 91 inFIGURE 11. A re-plot of FIGURE 11 on FIG- URE 9 shows that the totalcurrent is approximately 0.56 ma. through the diodes which is sufficient(above the valley point) to hold diode 40 in its high voltage state butinsufficient to trip diode 48 and produce a significant output. Thevoltage drop will cause a small negative going change in the output asthe current in diode 48 decreases from about .61 ma. to about .56 ma.(point 93 of FIGURE 3) of about .003 volt.

It has now been demonstrated that if a signal occurs in the first inputcircuit 67, no output will be produced; that if both signals arepresent, with signal 35 occuring first, no output will be produced, andfinally, if signal 35 goes off in the presence of signal 44, as would bethe case if signal 35 were higher in frequency, no output will beproduced.

At the end of the cycle just described, input signal 44 will go negativeat point 94 (FIGURE 1) for /2. cycle at the frequency of signal 44returning diode 40 to its original low voltage state for the duration ofthis negative pulse extending in time to point 96. At the nextup-crossing of the axis of input signal 44, diode 40 will again beswitched to its high voltage state by signal 35, provided first signal35 is present, and the events discussed above will repeat. If a firstsignal pulse of signal 35 is not present at the up-crossing of signal 44(a positive pulse of signal 44 occurs before a pulse of signal 35) diode40 will not be tripped until a pulse of signal 35 occurs and the stateof diode 40 will then have no significance. This is demonstrated in thefollowing discussion.

If positive signal 44 occurs in the absence of and thus leads signal 35,diode 48 will be raised to its high voltage state 97. The total currentthrough the diodes resulting from the bias and signal 44 is plotted inFIG- URE 11. Re-plots of curve 91 of FIGURE 11 on the tunnel region ofdiodes 40 and 48 given in FIGURES 2 and 3, respectively, show that diode48 will be raised to its high voltage state but diode 40 (at point 98)will not. The high voltage state voltage across diode 48 appears atcurve intersection (FIGURE 3) to be about .48 volt. This voltage willappear on the output as a significant signal pulse having a rise of fromabout .01 volt (point 77) to .48 volt which will be amplified andcounted by counter 58.

If pulse signal 35 appears in the presence of pulse signal 44 there willbe three sources of current on diode 40 and it will be raised to itshigh voltage state. It is now necessary to show that diode 48 remains inthe high voltage state maintaining the signal output. The voltage acrossdiode 40 as a result of signal 44 is shown as curve 99 in FIGURE 12, asa result of the bias supply it is shown as curve 100 in FIGURE 13 and asa result of signal 35 it is shown as curve 66 in FIGURE 5. The totalcurrent through diode 40 is plotted as curve 101 in FIGURE 14 andreplotted on the forward conduction portion of the curve for diode 40 inFIGURE 2 to show an intercept point 103 at approximately 0.5 volt. Oncein the high voltage state, the voltage drop across diode 40 will be aminimum of 0.49 volt due to the current flow from signal 44. Therefore,we can treat diode 40 as a fixed supply 40(a) of 0.49 volt (plusadditional drop on the linear portion of the forward conduction regionof diode 40 due to current from the second input signal 44) in serieswith diode 48 as shown in curves 105 (FIG- URE 15) and 106 (FIGURE 16).FIGURES l5 and 16 give the new current through diode 48 due to thecurrent from the second signal 44 and bias supply, respectively. Thetotal current through diode 48 is then plotted in FIGURE 17 as curve 108and replotted on the conduction curve for diode 48 in FIGURE 3. As shownin FIGURE 3 at point 110, the output voltage has decreased to 0.42 voltbut since the current through diode 48 is greater than the valley pointcurrent, (at point 112) diode 48 will remain in a high-voltage state.The circuit output has dropped by 0.060 volt. This is small and,. it isrelatively simple to adjust the sensitivity of output responsive devicessuch as counter 58, to which the output of diode 48 is fed, to beunresponsive to this change in view of the amplitude of maximum outputwhich is about eight times this value.

When signal 35 disappears in the presence of signal 44 both diodes willremain in their high voltage states due to the current from signal 44and the bias source, however, the voltage drop 48(a) across diode 48will rise slightly. The current through diodes 40 and 48 is plotted ascurve 91 in FIGURE 11 and replotted in FIG- URE 18, which is a plot ofthe combined voltage drops of diodes 40 and 48 in their high voltagestate. The intercept is at 0.66 ma., and this may be taken as thecurrent flowing through both diodes. Referring to FIGURE 3, it will beseen that the voltage drop corresponding to this current, at point 113,is approximately 0.45 volt; a rise of 0.025 volt.

The output to counter 58 will thus fluctuate between 0.42 and 0.45 volt(approximately) with the signal 35 for the duration of the positiveportion of input signal 44.

At the conclusion of the positive portion of signal 44, diode 48 willreturn to its low voltage state removing the output signal. Diode 40will return to its low voltage state at the next down-crossing of signal35 and both diodes will remain in their low voltage states for theduration of the negative half-cycle of signal 44.

The output signals are summarized in FIGURE 19 for the case where apositive pulse (I of signal 44 lags a positive pulse (I of signal 35,and in FIGURE 20 for the case where a pulse of signal 35 lags a positivepulse of signal 44. A 25 nanosecond seconds) lead or lag between signalshas been assumed for this illustration and the frequencies are assumedto be 10 Inc. for signal 35 and 1 me. for signal 44. For clarity, riseand switching times have not been plotted, but these are on the order of1 or 2 nanoseconds for the diodes set forth as examples above.

The significance of the effect of the time positions of I, and I ismanifest. In FIGURE 19., I lags I and a significant output responsive toI is inhibited, whereas in FIGURE 20 with I leading 1 there is a circuitoutput responsive to I which is quite significant and detectable bycounter 58. By intentionally introducing a known time delay, by delayline 37, the occurrence of the output of generator 36 may be adjustedwith respect to generator output 44 and pulses counted by the circuit ininstances where 1 actually lags the positive pulse output of generator36 and thus lead or lag conditions observed. If a fixed phase delay of aknown amount is introduced, we ar in effect, measuring the number 'oftimes during any convenient interval of time that the shift in phase ofthe signal from source 2 exceeded that delay. Thus if a number of delaysettings are used in succession and a count obtained for each, we willobtain 6 a statistical distribution for the short term phase behavior ofthe signal.

Alternately we may use the device for precise measurement of extremelysmall phas differences by means of a calibrated delay line and a rapidseries of go/no-go tests.

It is to be observed that while the present invention affords anexcellent means of phase comparison of like frequencies, if automaticrecording of changing response (phase stability) is required, theeffective frequency limit of counter 58 is greatly extended bytwo-frequency signal sampling of the character described. Accordingly,the implicit feature of signal gating is made adjustable to make moreversatile the employment of the invention.

There appears to be a number of other applications for the invention inthe general field of event detection and phase measurement. For example,delay-lock-loops are currently being proposed for long range radarsystems. Such a loop provides an extremely narrow band signaltrackingfilter in a manner similar to the conventional phase-lock-loop exceptthat output signals remain phase coherent. Unfortunately, the electronicphase shifters necessary for this technique have neither the precisionnor frequency capability necessary for modern radar applications.However, banks of fixed phase shift elements and high speed switchingmight be used in lieu of phase shifters if a suitable detector andswitching elements were available. In other words, the requirement wouldbe digitized .and phase shift would be controlled by a series ofgo/no-go tests. This invention performs exactly this function. In thisuse a number of the circuits would be required and the input signalwould be passed through parallel paths consisting of arbitrary phaseshifts. The proper delay would then be selected and routed to the delaylock loop.

Another example of use is in analog to digital conversion of phaseinformation. The most prevalent technique is the gating of a simplepulse train. Precise control of gate width is difiicult and the methodis subject to error due to circuit limitations such as gate slope. Anensemble of phase detectors as herein disclosed would be used to give amore precise digital readout on a cycle by cycle basis. For thisapplication the reference phase shift of each detector would be adjustedso that signals occur progressively later for each detector. The testinputs and the output terminals would then be tied together by suitableisolation circuits. If the output of each detector was firstdifferentiated the number of pulses would be a direct indication of theamount of phase shift necessary to balance the test signal.

Still another example of use was discovered during operation of theinvention when it was noted that very small differences in line lengthson the two inputs could be readily resolved by supplying both inputsfrom a single sourc through the test lines. This simple test setup isanalogous to interferometer measurements.

Obviously, many other modifications and variations of the presentinvention are possible in the light of the above teachings. It is,therefore, to be understood that within the scope of the appended claimsthe invention may be practiced other than as specifically described.

What is claimed is:

1. A phase detector for comparing the phase relationship between a firstinput signal and a second input signal, said first input signal being aseries of regularly recurring positive polarity pulses and said secondinput signal being a series of alternating pulses, the frequency of saidfirs-t input signal being an integral multiple of the frequency of saidsecond input signal, said phase detector comprising: a first tunneldiode connected between a first input terminal and ground; a secondtunnel diode connected between a second input terminal and said firstinput terminal, said second tunnel diode having a peak currentcharacteristic of approximately one half the peak 7 currentcharacteristic of said first tunnel diode; biasing means connectedacross said first and second tunnel diodes for biasing said tunneldiodes in their first positive resistance regions; first means forapplying said first input signal to said first input terminal; secondmeans for applying said second input signal to said second inputterminal, whereby said second tunnel diode is switched to its highvoltage region only when said second input signal leads said first inputsignal in phase; and output means connected across said second tunneldiode for sensing voltage rises thereacross, thereby to provide anoutput indicating that said second input signal leads said first inputsignal in phase.

2. A phase detector as described in claim 1 wherein the integralmultiple of the frequency of said first input signal with respect to thefrequency of said second input signal is one.

3. A phase detector as described in claim 1- wherein said first meansfor applying said first input signal in cludes an adjustable phase delaywhereby the phase relationship between said first input signal and saidsecond input signal may be varied by adjustment of said adjustable phasedelay.

4. Apparatus for detecting the phase. relationship be tween a firstinput signal and a second input signal, said first input signal being aseries of regularly recurring positive polarity reference pulses andsaid second input signal being a series of alternating pulses, thefrequency of said first input signal being an integral multiple of thefrequency of said second input signal, comprising in com bination: afirst nonlinear circuit including a first tunnel diode connected betweena first input terminal and ground; a second nonlinear circuit includinga second tunnel diode connected between a second input terminal and saidfirst input terminal, said second tunnel diode having a peak currentpeak characteristic of approximately one half the current peakcharacteristic of said first tunnel diode; biasing means connectedacross said first and second tunnel diodes for biasing said tunneldiodes in their first positive resistance regions; means for applyingsaid positive polarity reference pulses to said first input terminal,and means for applying said alternating pulses to said second inputterminal, whereby said second. tunnel diode is switched to its highvoltage region only for the duration of the positive portion of eachalternating; pulse which leads in phase the positive polarity referencepulses; and

counter means connected across said second tunnel diode ARTHUR GAUSS,Primary Examiner.

JOHN W. HUCKERT, Examiner.

8/1964 Hill et al. 30788.5.

1. A PHASE DETECTOR FOR COMPARING THE PHASE RELATIONSHIP BETWEEN A FIRSTINPUT SIGNAL AND A SECOND INPUT SIGNAL, SAID FIRST INPUT SIGNAL BEING ASERIES OF REGULARLY RECURRING POSITIVE POLARITY PULSES AND SAID SECONDINPUT SIGNAL BEING A SERIES OF ALTERNATING PULSES, THE FREQUENCY OF SAIDFIRST INPUT SIGNAL BEING AN INTEGRAL MULTIPLE OF THE FREQUENCY OF SAIDSECOND INPUT SIGNAL, SAID PHASE DETECTOR COMPRISING: A FIRST TUNNELDIODE CONNECTED BETWEEN A FIRST INPUT TERMINAL AND GROUND; A SECONDTUNNEL DIODE CONNECTED BETWEEN A SECOND INPUT TERMINAL AND SAID FIRSTINPUT TERMINAL, SAID SECOND TUNNEL DIODE HAVING A PEAK CURRENTCHARACTERISTIC OF APPROXIMATELY ONE HALF THE PEAK CURRENT CHARACTERISTICOF SAID FIRST TUNNEL DIODE; BIASING MEANS CONNECTED ACROSS SAID FIRSTAND SECOND TUNNEL DIODES FOR BIASING SAID TUNNEL DIODES IN THEIR FIRSTPOSITIVE RESISTANCE REGIONS; FIRST MEANS FOR APPLYING SAID FIRST INPUTSIGNAL TO SAID FIRST INPUT TERMINAL; SECOND MEANS FOR APPLYING SAIDSECOND INPUT SIGNAL TO SAID SECOND INPUT TERMINAL, WHEREBY SAID SECONDTUNNEL DIODE IS SWITCHED TO ITS HIGH VOLTAGE REGION ONLY WHEN SAIDSECOND INPUT SIGNAL LEADS SAID FIRST INPUT SIGNAL IN PHASE; AND OUTPUTMEANS CONNECTED ACROSS SAID SECOND TUNNEL DIODE FOR SENSING VOLTAGERISES THEREACROSS, THEREBY TO PROVIDE AN OUTPUT INDICATING THAT SAIDSECOND INPUT SIGNAL LEADS SAID FIRST INPUT SIGNAL IN PHASE.